The present invention relates to the field of amplifier and comparator circuits which are implemented utilizing a differential amplifier. More particularly, the present invention relates to the field of amplifier and comparator circuits utilizing a differential amplifier and having a controllable output offset.
Differential amplifiers are commonly utilized for amplifying signals and for comparing signal levels. FIG. 1 illustrates a conventional differential amplifier circuit. A high potential supply Vcc is coupled to a source of a PMOS transistor M1 and to a source of a PMOS transistor M2. A drain of the transistor M1 forms an inverting output terminal of the differential amplifier and is coupled to a drain of an NMOS transistor M3. A drain of the transistor M2 forms a non-inverting output terminal of the differential amplifier and is coupled to a gate of the transistor M1, to a gate of the transistor M2 and to a drain of an NMOS transistor M4. A gate of the transistor M3 forms a non-inverting input of the differential amplifier, while a gate of the transistor M4 forms an inverting input of the differential amplifier. A source of the transistor M3 and a source of the transistor M4 are coupled together and to first terminal of a current source I1. A second terminal of the current source I1 is coupled to a low potential supply Vss.
The current source I1 provides bias current for the transistors M1, M2, M3 and M4. An input signal Vin+ is applied to the gate of the transistor M3, while an input signal Vinxe2x88x92 is applied to the gate of the transistor M4. Together, the signals Vin+ and Vinxe2x88x92 form an input differential signal [(Vin+)xe2x88x92(Vinxe2x88x92)]. In response to the input differential signal, an output signal Vout1 is formed on the output terminal of the differential amplifier. Over a limited range of values for the input differential signal, the output signal Vout1 is representative of the input differential signal multiplied by a gain factor of the differential amplifier. Under such conditions, the differential amplifier acts as a linear amplifier. Outside this limited range of input values, the output Vout1 of the differential amplifier reaches a limiting value [i.e. nearly (Vcc) or (Vss)], depending upon the relative levels of the signals Vin+and Vinxe2x88x92. Under such conditions, the differential amplifier acts as a level comparator.
When the input signals Vin+ and Vinxe2x88x92 are equal, then the input differential signal is zero. Under such conditions, the output signal Vout1 should also be zero. In practice, however, the output Vout1 is typically non-zero. The output voltage formed when the input differential voltage is zero is known as output offset voltage. The output offset voltage is typically caused by process variations in the transistors which form the differential amplifier. When the differential amplifier is utilized as a linear amplifier, the output offset contributes to errors in the level of the output signal Vout1. When the differential amplifier is utilized as a level comparator, the output offset can result in the output Vout1 incorrectly indicating the result of the comparison, especially when the signal levels to be compared are close in value. Therefore, the output offset is ideally zero.
Initial adjustment procedures are typically undertaken during the manufacture of an integrated circuit which includes a differential amplifier in order to reduce or eliminate the output offset voltage of the differential amplifier. For example, fuses are blown or laser trimming is employed in order to adjust resistance values of load resistors placed in series with the transistors of the differential amplifier. An alternate approach has been to include one or more pins in the integrated circuit by which the output offset voltage is adjusted by resistor selection or potentiometer adjustment at the time of printed circuit board manufacture. However, the output offset voltage may vary over time, and with temperature and supply voltage levels, thereby reducing the effectiveness of these initial adjustment techniques.
Another prior technique for reducing the output offset voltage has been to provide a voltage source which adds to or subtracts from the input differential signal. For example, a first terminal of the voltage source receives the input voltage Vin+ (FIG. 1), while a second terminal of the voltage source is coupled to the gate of the transistor M3 (FIG. 1). The output signal Vout1 can be fed back through an integrator to adjust the voltage source in such a manner as to reduce or eliminate the output voltage offset. This technique has a drawback in that it can be difficult to implement.
Therefore, what is needed is an improved technique for reducing or eliminating the output offset voltage of a differential amplifier.
The invention is an apparatus for and a method of controlling amplifier output offset using body biasing in MOS transistors. An amplifier in accordance with the present invention includes a differential input stage having a pair of input MOS transistors. The pair of input MOS transistors are formed having isolated bodies. A differential input signal is applied across the gates of the input MOS transistors. Each of the input MOS transistors is appropriately biased and loaded. More particularly, the input MOS transistors are preferably NMOS transistors whose drains are coupled to a pair PMOS transistors. The pair of PMOS transistors are coupled to a high potential supply and form an active load for the input NMOS transistors. A first current source coupled to the sources of the input NMOS transistors and to a low potential supply serves to bias the input NMOS transistors.
An output of the amplifier is derived from a voltage formed at the drain of one of the input MOS transistors. More particularly, a single-ended output stage of the amplifier includes an output transistor where a gate of the output transistor is coupled to the drain of one of the input MOS transistors. The output transistor is preferably a PMOS transistor whose source is coupled to the high potential supply and whose drain is coupled to a second current source. The second current source biases the output transistor. An output node for the amplifier is formed at the drain of the output transistor.
A feedback loop includes an integrator and a feedback amplifier. The integrator receives an output signal from the output node and integrates the output signal, thereby forming an integrated output signal. The integrated output signal is applied to a first input of the feedback amplifier, while a reference voltage is applied to a second input of the feedback amplifier. The reference voltage is representative of a desired quiescent or dc level for the output signal. An output of the feedback amplifier is coupled to control the voltage of the body of one of the pair of input MOS transistors. The body of the other one of the pair of input MOS transistors is preferably coupled to its source.
According to the present invention, the threshold voltage of the input transistor having its body coupled to the feedback amplifier is controlled in such a manner as to reduce or eliminate the offset voltage. More particularly, assume that the gate of input transistor having its body coupled to the feedback amplifier is a non-inverting input of the amplifier. In which case, when the integrated output signal is lower than the reference voltage, the feedback loop will tend to increase the voltage applied to the body of the input transistor having its body coupled to the feedback amplifier. As a result, the output voltage tends to rise, which tends to increase the integrated output signal. Conversely, when the integrated output signal is higher than the reference voltage, the feedback loop tends to reduce the voltage applied to the body of the input transistor having its body coupled to the feedback amplifier. As a result, the output voltage tends to fall, which tends to reduce the integrated output signal. Thus, a quiescent or dc level of the output signal tends to be equal to the level of the reference voltage. This quiescent or dc level can be set to zero volts or to a non-zero level. A time constant associated with the feedback loop is sufficiently long that frequencies of interest for the input differential signal pass to the output of the amplifier after being amplified according to its gain and without affecting the bias voltage formed by the feedback loop.
A comparator in accordance with the present invention differs from the amplifier described above in that the integrator and feedback amplifier are omitted and, instead, a second reference voltage is applied directly to the body of the input transistor having its body voltage controlled. The offset voltage is reduced or eliminated by adjusting the second reference voltage. The signals to be compared are applied to the gates of the input transistors. Because the offset voltage is reduced, the output voltage accurately represents the relative levels of the input signals, even when the signals to be compared are close in value.